Logic technologies such as very large scale integrated circuits provide significant improvements in cost/performance and reliability. However, they have disadvantages in that their fault diagnosis is more difficult than previous technologies and their engineering rework cycles needed to correct faults in logic design are greatly lengthened. These disadvantages exact great economic penalties for design errors and omissions and place a great emphasis on the goal of completely verifying designs in advance of engineering models.
One technique for providing design verification is logic simulation by a general purpose computer. Another technique is to use a special purpose computer that is optimized for logic simulation. The special purpose computer usually uses a multiple processor architecture by which a number of processors, called simulation processors, may be interconnected to improve simulation performance. The special purpose computer may operate in combination with a host computer which is used to provide several services, for example, loading functions, memory modeling, analysis on the results of the simulation, user interface, etc. Such a special purpose computer is called a logic simulation machine. The invention relates to a host interface of the logic simulation machine for connecting the logic simulation machine to the host computer.
The prior art logic simulation machine is described in U.S. Pat. No. 4,306,286 issued Dec. 15, 1981, to Cocke et al. and assigned in common with the present application. The logic simulation machine of the Cocke et al. patent comprises a plurality of parallel basic processors which are interconnected through an inter-processor switch. The inter-processor switch provides communication not only among the basic processors which are computing engines of the logic simulation machine, each simulating the individual gates of a portion of a logic model in parallel, but also between them and a control processor which provides overall control and input/output facilities of the logic simulation machine through a host computer to which the control processor is attached. Each basic processor contains the current state information for only the set of gates that is being simulated by that processor. When a basic processor simulates a gate whose input includes a connection to the output of a gate being simulated by a different processor, the state information for the gate in question is transferred over the inter-processor switch.
The host computer provides the logic simulation machine with several services, loading function, memory modeling, analysis on the results of the simulation, user interface, etc. In order to provide such services, communication between the host and the logic simulation machine needs to be established. The communication, however, causes delays in the simulation due to host-machine interaction when the communication is established during the simulation. Namely, the logic simulation machine is required to stop during host interactions, slowing down the net simulation throughput. There is no teaching in the Cocke et al patent directed to utilizing First-In First-Out buffers for the interface between the host and the logic simulation machine to minimize the delays.